1. Field of the Invention
This application relates to integrated circuit devices more particularly to integrated circuits utilized in generating clock signals and systems incorporating such circuits.
2. Description of the Related Art
Clock sources typically utilize a resonator such as a crystal oscillator or surface acoustic wave (SAW) device. Precision in traditional clock sources utilizing crystal oscillators is determined by the accuracy of the cut of the crystal and the calibration performed after the cut. For example, frequency tuning may be achieved by sputtering gold after cutting the crystal. Fixed frequency sources such as crystals have typically provided better phase noise performance than the phase noise performance associated with variable frequency source such as, e.g., a voltage controlled oscillator (VCO). That is due, at least in part, to the fact that the variable elements (e.g., the varactor) associated with the VCO used to vary the frequency have higher losses than fixed elements such as the capacitors in a fixed source.
However, resonators typically have a limited optimum range due to manufacturing constraints. That is, it is hard to pull a crystal over a wide range. However, various applications have requirements for numerous frequencies outside the easy range for a resonator. Typically, a different frequency range will require a different resonator. Accuracy requirements vary for clock sources, but are typically in the parts per million (ppm) range.
The drive to design network equipment with multi-service capable interfaces has dramatically increased the complexity of the timing subsystems. In addition to standard SONET/SDH rates, these new systems must now support a diverse set of line rates including 10 G Ethernet, 10 G Fibre Channel, as well as the associated forward error correction (FEC) rates. Requirements to support these new data rates is forcing timing subsystem designers to develop timing sources capable of providing an expanded set of low jitter, high frequency (>=622 MHz) reference clocks for use across the data processing chain from physical layer to backplane transceiver. A summary of common line rates and the associated board level reference clock frequencies is provided in Table 1. Since these frequencies are not related by a simple integer ratio, designers must rely on multiple discrete oscillators or sophisticated phase-locked loops (PLLs) to support the various reference clock generation requirements in multi-protocol systems. Note that many of the line rates are around 10 Gbits per second.
TABLE 1ForwardRequiredDataErrorLineOscillatorRateCorrectionRateFrequenciesProtocol(Gbps)(FEC) Ratio(Gbps)(MHz)SONET OC-192,9.95—9.95622.08, 155.52SDH STM-64G.975 (4 ×9.95255/23810.66666.51, 166.63OC-48 + FEC)OTN OTU29.95255/23710.71669.33, 167.33(G.709)10 Gb10.31—10.31644.53, 161.13Ethernet LAN10.31255/23811.04690.57, 172.6410.31255/23711.10693.48, 173.3710 G Fibre10.52—10.52657.42, 164.35Channel10.52255/23711.32707.35, 176.83
Using conventional oscillator technology, the system timing architectures of multi-service systems become unwieldy as the number of oscillators grow to support an expanded set of line rates. FIG. 14 illustrates a Dense Wavelength Division Multiplexing (DWDM) transponder (dual facing (forward error correction (FEC) line cards). As shown in FIG. 14, the clock and data recovery circuit (CDR) in the receive path of each 10 G transceiver requires a reference clock frequency that is an integer sub multiple of each line rate. To meet this requirement, RF multiplexers 1401, 1403 are typically used to select the appropriate reference clock from a bank of oscillators 1405, 1407 whose frequencies are associated with the desired set of line rates. In the example illustrated in FIG. 14, the provided oscillator bank supports transponder operation at four different line rates: OC-192, OTU-2, 10 GbE LAN, and 10 GbE LAN+FEC. In order to support the different line rates, both XO bank 1409 and the VCXO banks 1405 and 1407 are required. A separate crystal or SAW resonator is associated with frequency in the illustrated transponder. Thus, for example, in the example illustrated in FIG. 14, 12 separate crystals/SAW resonators are required.
The clock scaling PLLs 1412, 1414 are the most critical timing subsystem because they must perform the clock scaling required to synchronize the data transmission rates between the client side and the line side. The design of these PLLs is difficult because they must provide non-integer clock scaling, operate at high frequencies (>600 MHz), provide low jitter (<0.3 ps RMS), and cover a range of frequencies that span approximately 100 MHz. To meet the jitter requirements, discrete voltage controlled SAW oscillators (VCSOs) or high frequency fundamental (HFF) voltage controlled oscillators (VCXOs) must be used in the PLL circuit. Since these devices are only capable of operating within a few hundred parts per million (ppm) of a center frequency, multi-protocol support requires a bank of VCSOs or VCXOs to support the range of input to output frequency translations required. In addition, special care must be taken during the design and layout of the PLL circuit to accommodate variations in VCSO electrical performance like voltage gain (Kv) and prevent noise coupling between VCSOs and other board level components.
Since traditional oscillator technology does not scale easily to support additional line rates, the system implication is one of increased cost, board space, bill-of-materials (BOM), and supply issues. In addition, these crystal and SAW based oscillators introduce various reliability issues including temperature drift and long term aging. While the frequency control industry has made some progress supporting dual frequency applications by packaging multiple resonators into a single VCSO module package, the techniques employed are difficult to scale beyond two frequencies.
It would also be desirable to provide a clock source that meets accuracy requirements, allows the use of a resonator that is easy to manufacture and low cost, but can still provide a wide range of output frequencies and suitable phase noise performance.